Meta is accelerating its custom artificial intelligence chip program as it seeks greater control over the cost, performance and deployment speed of the computing systems behind Facebook, Instagram and its growing portfolio of generative-AI services.

The company’s Meta Training and Inference Accelerator, or MTIA, roadmap now covers four successive processors scheduled for production or deployment during 2026 and 2027. Meta says the program can deliver a new chip approximately every six months, compared with the one- or two-year development cycles that commonly characterize advanced AI processors.

That faster schedule is central to Meta’s strategy. AI models, inference techniques and memory requirements can change significantly while a conventional processor is still being designed and manufactured. Meta is attempting to shorten that gap by reusing modular components and keeping successive processors compatible with the same physical infrastructure.

MTIA 300, the first processor in the new sequence, is in production for training the ranking and recommendation systems that select posts, advertisements and videos across Meta’s platforms. Those workloads remain commercially important because they directly affect user engagement and advertising performance.

MTIA 400 expands the architecture toward generative AI while retaining support for recommendation workloads. Meta says laboratory testing has been completed and the processor is moving toward data-center deployment. A rack-scale configuration connects 72 MTIA 400 accelerators within one scale-up domain, allowing them to operate collectively on larger models and data sets.

The following generations are more explicitly focused on generative-AI inference—the process of running an already trained model to answer prompts, generate media or deliver other AI-powered services. Meta expects inference demand to rise sharply as AI features reach more users across its applications.

MTIA 450 is scheduled for mass deployment in early 2027. Meta says it doubles high-bandwidth-memory throughput from MTIA 400 and adds hardware designed to improve attention operations and mixture-of-experts computations. The chip also supports lower-precision numerical formats intended to increase processing efficiency without materially degrading model quality.

MTIA 500, planned for deployment later in 2027, is designed to extend those gains. Meta says it will provide 50% more memory bandwidth than MTIA 450, as much as 80% additional memory capacity and 43% higher performance for certain low-precision calculations.

Across the full progression from MTIA 300 to MTIA 500, Meta projects a 25-fold increase in compute capability and a 4.5-fold increase in high-bandwidth-memory throughput. Those figures are company specifications rather than independent performance measurements, and real-world results will depend on the models, software and system configurations used.

Meta’s approach differs from the design philosophy behind many general-purpose GPUs. Commercial accelerators are frequently optimized for computationally intensive model training and then used for a much broader range of tasks. Meta is starting with inference and other workloads it can forecast internally, allowing it to remove capabilities that may be unnecessary for a particular deployment.

Specialization can improve performance per dollar and performance per watt, two increasingly important measures as AI data centers consume more capital and electricity. It can also create limitations. A processor optimized for recommendations or inference may be less useful when engineering teams need to redirect capacity toward frontier-model training or an unexpected architecture.

Meta is addressing that risk through a portfolio rather than an all-or-nothing transition. The company continues to buy large quantities of accelerators from Nvidia and AMD while developing internal hardware with Broadcom and relying on Taiwan Semiconductor Manufacturing Co. for fabrication.

Recent reporting illustrates how customized external chips fit into the same plan. Tom’s Hardware, citing analysis from SemiAnalysis, reported that an AMD accelerator tailored for Meta could use 144 gigabytes of HBM4 memory, one-third of the capacity associated with AMD’s full MI455X product. The reported configuration would target recommendation systems, potentially lowering component costs and power consumption while sacrificing versatility. The specifications have not been formally detailed by Meta or AMD.

Separately, Reuters reported earlier in July that Meta intends to begin manufacturing an internally designed data-center chip, code-named Iris, in September. An internal memorandum reviewed by Reuters said testing was completed in about six weeks without major problems. Broadcom is assisting with the design, while TSMC is expected to manufacture the processor.

The Iris milestone suggests Meta’s six-month development target is moving beyond a public roadmap. It also reflects the company’s broader effort to scale computing capacity quickly while reducing delays associated with deploying the newest commercial GPUs across enormous data-center fleets.

Software compatibility may determine whether the hardware schedule succeeds. Custom processors can deliver attractive theoretical efficiency but fail to gain broad internal use when developers must rewrite models, kernels and deployment tools. Meta is attempting to limit that friction by building MTIA around PyTorch, vLLM, Triton and Open Compute Project standards.

The company says models can be moved between GPUs and MTIA without MTIA-specific rewrites in many cases. Its compiler stack uses technologies including TorchInductor, Triton, MLIR and LLVM, while production tools provide monitoring, profiling and debugging across hardware, firmware and software.

Physical compatibility is another part of the strategy. MTIA 400, 450 and 500 are designed to use common chassis, rack and networking infrastructure. Rather than replacing an entire data-center system for every generation, Meta can upgrade selected chiplets or accelerators while preserving more of the surrounding equipment.

That modularity helps explain how Meta expects to release processors more frequently. It may also reduce deployment risk by allowing new generations to enter service incrementally instead of requiring a single large architectural transition.

Meta’s claim of greater hardware self-reliance therefore requires qualification. The company is gaining more control over processor architecture, workload optimization and deployment timing, but it still depends on outside partners for design assistance, fabrication, memory, packaging and general-purpose GPUs. Its strategy is less about complete independence than about avoiding dependence on one type of chip or one supplier.

For Silicon Valley’s AI industry, the broader signal is that software platforms are becoming hardware portfolio managers. Meta, Google, Amazon and Microsoft increasingly combine internally designed accelerators with commercial processors, networking systems and software frameworks selected for specific workloads.

Meta’s advantage is the scale and predictability of its internal demand. It can design chips for recommendation engines and AI services that operate across billions of users, then deploy those processors in volumes large enough to justify development costs. Whether MTIA becomes a lasting competitive advantage will depend on production yields, software adoption, reliability and the economics of operating the chips at scale.

The four-generation roadmap nevertheless marks a clear change in ambition. Meta is no longer treating custom silicon as an isolated experiment. It is building a recurring hardware pipeline intended to evolve alongside its models, reduce infrastructure bottlenecks and give the company more control over one of the most expensive layers of the AI business.